How can I build an S-R latch using only positive-edge triggered D Flip Flops?

I need to design an S-R latch using only a single, 74x74 positive edge triggered D flip flop.

How can I build an S-R latch using only positive-edge triggered D Flip Flops?
I don't think it can be done, (but I maybe wrong).
Reply:I'm assuming that your set and reset signals are active-high and mutually exclusive.





I can't say that I've actually tried this, but you could try feeding the clock pin of the D-flop with the logical "NOR" of the set and reset signals. The falling edge of either signal will act as a rising clock edge. Then feed the data pin of the D-flop directly with the set signal. Thus, when the set signal is asserted and then de-asserted, the D-flop will latch logic "1". If the reset signal is asserted and then de-asserted, the D-flop will latch logic "0". This gets slightly more complicated if set and reset can occur at the same time. In that situation, you need to determine which will have priority before determining how to design the circuit to feed the data pin of the D-flop.





The reason for using the falling edges of the set and reset signals to clock the D-flop is to avoid a race condition between the clock and data pin (known as the data setup time in static timing analysis). The caveat, of course, is that you have to de-assert the set or reset signal before the D-flop will capture the desired value, so it's not exactly a true S-R latch.



acne care