Analysis of Sequential Circuits - T Flip-flops -?

A T flip-flop is implemented using a J-K master-slave flip-flop that changes state on the falling edge of


the clock. Assume that the circuit is fabricated using NAND gates with a 1 ns propagation delay.


a) Determine the set-up, Tsu, hold, Th, and propagation delay, Tpd, parameters for this flipflop. Create the circuit.





b) Compare the behaviour of a rising edge T master-slave flop-flop circuit (made from part a, in other


words, made from a falling edge T MS flip-flop) to a rising edge-triggered T flop-flop.

Analysis of Sequential Circuits - T Flip-flops -?
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http://en.wikipedia.org/wiki/Flip-flop_(...



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